The present invention relates generally to floating-point processing systems and, more particularly to processing merged floating-point operations.
The ever shrinking dimensions of feature sizes on integrated circuits has enabled the integration of more circuits on the same silicon die at no additional cost. Such circuits have enabled new integrated circuit functionality thus leading to greater flexibility and enhanced computing capability.
Modern processor computing systems can execute a multitude of operations within their Instruction Set Architecture (ISA). Some processor ISAs perform floating-point arithmetic operations involving a wider range of values than can be supported by fixed-point or integer representation. Floating-point values are represented by a multitude of significant digits, called a significand, multiplied by a base raised to the power of an exponent. The number of significant digits in the significand is related to the precision of the value stored in the floating-point processing system.